1. Field of the Invention
The present invention relates generally to semiconductor packages, and, more particularly, to a method and apparatus for electrical connection of a semiconductor die in a semiconductor package using the package lid.
2. Description of the Related Technology
In order to facilitate handling and connection of a semiconductor die to external systems, a common practice in the semiconductor industry is to package the die. Die packaging usually involves mechanically and electrically attaching a die to a package case and sealing the die in or on the package case to form a semiconductor device assembly.
For example, a package case may be constructed from ceramic, printed circuit board (PCB), epoxy laminates, or the like. The package case has a central die receiving area or cavity on one face, and bond fingers or the like located on the package case face surrounding the periphery of the die receiving cavity. A die is centrally mounted in the die receiving cavity and bond pads on the die are electrically connected using bond wires or the like to the respective bond fingers on the package case. The bond fingers exit the package case, and usually terminate in external connectors such as ball bumps, pins or the like (hereinafter external connectors). The external connectors may be located on a single planar surface of the package case. The die receiving cavity may be covered with an encapsulant glob top and/or a package lid, thereby forming a sealed package body around the die and bond wires to minimize potential damage from environmental or mechanical harm. If a package lid is utilized, the package lid is attached to the package case, but the package lid does not physically contact either the die or the bond wires.
In some instances, where the die receiving cavity is on one face of the package case, and the external connectors are on an opposite face of the package case, the completed semiconductor device assembly is referred to as "cavity up". In other instances, where the die receiving cavity is on the same face of the package case as the external connectors, the completed semiconductor device assembly is referred to as "cavity down".
FIGS. 1a, 1b, 2 and 3 illustrate typical prior art semiconductor packages. FIGS. 1a, 1b and 3 illustrate "cavity up" construction. FIG. 2 illustrates "cavity down" construction.
Referring now to FIG. 1a, a prior art package case 102 with a mounted semiconductor die 104 is illustrated in schematic top view prior to sealing with a package lid 124 (illustrated in FIG. 1b). The die 104 is centrally located in the die receiving cavity 106 and mounted to the package case 102 using nonconductive epoxy 108 (illustrated in FIG. 1b). Bond pads 110 are located on the periphery of the active face of the die 104 and have a diameter 112 and center to center distance (hereinafter pad pitch) 114. A number of bond fingers 116, equal to the number of bond pads 110, are disposed on one layer (or tier) of the package case 102 proximate to the respective bond pads 110. The bond fingers 116 have a width 118 and a center to center distance (hereinafter finger pitch) 120. The finger pitch 120 is measured at the ends of the bond finger 116, located proximate to the die 104. The bond pads 110 are electrically connected in a one to one relationship to the respective bond fingers 116 by bond wires 122. For illustrative clarity, only a few of many such bond pads 110, bond fingers 116 and bond wires 122 are shown.
Referring now to FIG. 1b, a prior art cavity up sealed package body 100 is illustrated in schematic cross-section elevational view. The sealed package body 100 is formed when a package lid 124 is attached to the package case 102 of FIG. 1a thereby sealing the die 104, bond pads 110, bond wires 122, and bond fingers 116 in the die receiving cavity 106. The package lid 124 may be attached to package case 102 using nonconductive epoxy 126. The bond fingers 116 are electrically connected to respective vias 128 which electrically connect to respective traces 130 located on the opposite face of the package case 102. The traces 130 electrically connect the vias 128 to respective external connectors 132.
Referring now to FIG. 2, a prior art cavity down sealed package body 200 is illustrated in schematic cross-section elevational view. Similar to the cavity up sealed package body 100 illustrated in FIG. 1b, a semiconductor die 204 is centrally located in a die receiving cavity 206 in a package case 202. The die 204 is attached to the package case 202 using a nonconductive epoxy 208. Bond pads 210 located on die 204 are electrically connected to bond fingers 216 on the package case 202 using bond wires 222.
The bond fingers 216 are electrically connected to respective vias 228 which, unlike the vias in the cavity up sealed package body 100 illustrated in FIG. 1b, electrically connect to respective traces 230 and respective external connectors 232 located on the same face as the opening to the die receiving cavity 206. A package lid 224 covers the opening of the die receiving cavity 206 and may be attached to the package case 202 using a nonconductive epoxy 226 or the like.
Over the past few years the continuous advance in semiconductor die technology has provided a constant and dramatic increase in the number of circuits (i.e. circuit density) which could be incorporated into a semiconductor die of a given size. As the circuit density of a semiconductor die increases (hereinafter high density die), the number of bond pads on the high density die's active face must also increase. In order for all of the increased number of bond pads to lie near the high density die's periphery for connection to the bond fingers, the bond pad diameter and pad pitch must also be reduced.
In order to package a high density die having an increased number of bond pads, a package case must have a commensurate increase in bond fingers so that the bond pads can be attached in a one to one relationship with the bond fingers. Unfortunately, semiconductor packaging technology has not been able to match the size reductions achieved in semiconductor die technology. Although packaging technology has been able to reduce both bond finger width and finger pitch, finger pitch has proven to be a limiting factor in package case design. Because current semiconductor packaging technology has not been able to reduce finger pitch enough to allow the necessary number of bond fingers to be placed all in the same tier, so that the bond fingers could be attached on a one to one basis with bond pads on a high density die, semiconductor package cases were modified to include two or more tiers of bond fingers placed around and proximate to the periphery of the high density die.
Referring now to FIG. 3, a prior art lidded cavity up semiconductor package body for a high density die is illustrated in schematic cross-section elevational view. Similar to the semiconductor package bodies illustrated in FIGS. 1b and 2, the semiconductor package body 300 has a package case 302 with a centrally located die receiving cavity 306. A high density die 304 is centrally mounted in the die receiving cavity 306 using an epoxy 308. Unlike FIGS. 1b and 2 (though not illustrated the following is equally applicable to both cavity up and cavity down package cases) the package case 302 has a first tier of bond fingers 316a and a second tier of bond fingers 316b to accommodate an increased number of bond pads 310 on the high density die 304.
In all of the foregoing illustrations, a common element is that the bond pads are connected to the bond fingers in a one to one relationship. The one to one relationship is necessary to keep bond wire lengths to a minimum so as to minimize the possibility of the bond wires shorting against one another or breaking. Unfortunately, as the number of semiconductor bond pads increases, so does the number of associated bond fingers, and due to the limitation of bond finger pitch, the solution has been to stagger the deployment of bond fingers into additional tiers surrounding the die, thereby requiring additional bond wires of increasingly unacceptable length.
In addition to causing semiconductor device assemblies to experience catastrophic failures such as bond wire shorting or breaking, unacceptable bond wire length can also reduce or hinder overall performance efficiency of the semiconductor device assembly in several ways. For example, at unacceptable lengths bond wire resistance can become sufficiently large to cause excessive voltage drops between the respective bond pad and bond finger. Further, as the bond wire resistance increases, the possibility exists that the semiconductor die operation may be slowed due to resistive-capacitive delays when the unacceptably long bond wire(s) interact with parasitic capacitances within the semiconductor device assembly.
What is needed is a method and apparatus which will allow an increased number of semiconductor die bond pads to be electrically interconnected to a semiconductor package body while maintaining both a minimum number of required bond fingers and a minimum bond wire lengths in the completed semiconductor device assembly.